1. Field of the Invention
The present invention generally relates to a measurement method and circuit. More particularly, the present invention relates to a measurement method and circuit for measuring the capacitance and the capacitance mismatch of capacitor pairs.
2. Description of Related Art
Conventionally, in a semiconductor integrated circuit (IC), capacitor is an important component. In general, the statistic variation of the mismatch (or ratio) of the capacitances of capacitor pair is important for switched capacitor circuit techniques. Therefore, the measurement of the mismatch or the ratio of the capacitances of capacitor pair is highly desired.
In general, for a capacitor pair constructed by two capacitors, a conventional measurement method is provided by a capacitor matching method to measure the mismatch between the capacitances of two capacitors. FIG. 1 illustrates a conventional circuit for measuring a capacitance and a mismatch of the capacitances of two capacitors. Referring to FIG. 1, assume that a capacitor 102 to be measured has a capacitance C1 and another capacitor 104 to be measured has a capacitance C2. As shown in FIG. 1, PMOS transistor having a floating gate is used to measure the capacitance C1, C2 or the mismatch between the capacitance C1 and C2. The capacitance Cpar represents a parasitic capacitance between the gate and the drain of the PMOS transistor, and it will be proved that the mismatch between the capacitance C1 and C2 is not dependent on the parasitic capacitance Cpar. Referring to FIG. 1, a terminal of the capacitor 102 and a terminal of the 104 are connected to the floating gate of the PMOS transistor. The other terminal of the capacitor 102 is a voltage input terminal for inputting an input voltage Vin, and the other terminal of the capacitor 104 is connected to ground. The source of the PMOS transistor is connected to a current source 11, and the drain of the PMOS transistor is grounded.
The circuit of FIG. 1 may be provided to measure the capacitance C1 of the capacitor 102 when the capacitance C2 of the capacitor 104 is known. The measurement is adopted by applying at least two input voltages Vin_lo and Vin_hi from the voltage input terminal of the capacitor 104 and then to measure the output voltages Vout_lo and Vout_hi at the source of the PMOS transistor. Therefore, a slope S is obtained.
FIG. 2 illustrates a measurement result of the circuit shown in FIG. 1. Referring to FIG. 2, as described above, the slope S is:S=(Vout—hi−Vout—lo)/(Vin—hi−Vin—lo)=C1/(C1+C2)  (1)
Therefore, when capacitance C2 is known or given, the capacitance C1 can be measured.
In addition, the circuit of FIG. 1 can also be provided to measure the mismatch between the capacitance C1 and C2 by using the method shown in FIG. 2. Assume that ΔC represents the difference between the capacitance C1 and C2, i.e., ΔC=C1−C2, and C represent the average value of capacitance C1 and C2, i.e., C=(C1+C2)/2. It is noted that, the ratio of ΔC to C is:ΔC/C=2(C1−C2)/(C1+C2)=4(S−1/2)  (2)
Therefore, the mismatch ΔC/C of the capacitance C1 and C2 is obtained by the slope S measured by the method shown in FIG. 2.
Moreover, when the parasitic capacitance Cpar shown in FIG. 1 cannot be ignored, the circuit of FIG. 1 can also be provided for measuring the ratio ΔC/C. The measurement method includes the following steps. First, a first slope S1 is measured in the circuit shown in FIG. 1 by using the measurement method similar to FIG. 2, wherein S1 is:S1=C1/(C1+C2+Cpar)  (3)
The Cpar represents the parasitic capacitance shown in FIG. 1. Thereafter, since the capacitors 102 and 104 are disposed symmetrically, referring to FIG. 3, the capacitor 102 is grounded and the voltage input terminal of the capacitor 104 is connect to an input voltage Vin. Thus, a second slope S2 is measured by using the measurement method similar to FIG. 2, wherein S2 is:S2=C2/(C1+C2+Cpar)  (4)
Therefore, the ratio of ΔC to C is obtained by combining the equations (3) and (4):ΔC/C=2(C1−C2)/(C1+C2)=2(S1−S2)/(S1+S2)  (5)
Therefore, the ratio of ΔC to C is obtained by measuring the first slope S1 and the second slope S2 by using the measurement method similar to FIG. 2. It is noted that, the ratio ΔC/C is only dependent on the first slope S1 and the second slope S2, and is independent on the parasitic capacitance Cpar.
FIG. 4 illustrates a capacitor matching circuit of a conventional semiconductor integrated circuit (IC). Referring to FIG. 4, in general, when two capacitors 402a and 402b are measured, a PMOS transistor 406 and four pads 404a, 404b, 404c and 404d are required. Therefore, when a plurality of capacitor pairs are measured, it is noted that a lot of PMOS transistors and pads are required. The area required for the capacitor matching circuit is large since 4 pads are required for measuring each capacitor pair. Moreover, the pads connected and detected for the measurement are changed in each measurement. Thus, if the conventional capacitor matching circuit and method are provided for a semiconductor integrated circuit (IC), the measurement too complex to be enabled. Therefore, a measurement method and circuit suitable for measuring a plurality of capacitor pairs is quite desirable.